1. Field of the Invention
The present invention relates to a wafer handling system and method for use within a lithography system. More particularly, this invention relates to a system and method of wafer handling in which wafers are transported within a lithography system while being affixed and aligned to chucks, thereby maximizing production throughput.
2. Related Art
Lithography is a process used to create features on the surface of substrates. Such substrates can include those used in the manufacture of flat panel displays, circuit boards, various integrated circuits, and the like. A frequently used substrate for such applications is a semiconductor wafer. While this description is written in terms of a semiconductor wafer for illustrative purposes, one skilled in the art would recognize that this description also applies to other types of substrates known to those skilled in the art. During lithography, a wafer, which is disposed on a wafer stage, is exposed to an image projected onto the surface of the wafer by exposure optics located within a lithography apparatus. While exposure optics are used in the case of photolithography, a different type of exposure apparatus may be used depending on the particular application. For example, x-ray, ion, electron, or photon lithographies each may require a different exposure apparatus, as is known to those skilled in the art. The particular example of photolithography is discussed here for illustrative purposes only.
The projected image produces changes in the characteristics of a layer, for example photoresist, deposited on the surface of the wafer. These changes correspond to the features projected onto the wafer during exposure. Subsequent to exposure, the layer can be etched to produce a patterned layer. The pattern corresponds to those features projected onto the wafer during exposure. This patterned layer is then used to remove exposed portions of underlying structural layers within the wafer, such as conductive, semiconductive, or insulative layers. This process is then repeated, together with other steps, until the desired features have been formed on the surface of the wafer.
Step-and-scan technology works in conjunction with a projection optics system that has a narrow imaging slot. Rather than expose the entire wafer at one time, individual fields are scanned onto the wafer one at a time. This is done by moving the wafer and reticle simultaneously such that the imaging slot is moved across the field during the scan. The wafer stage must then be stepped between field exposures to allow multiple copies of the reticle pattern to be exposed over the wafer surface. In this manner, the sharpness of the image projected onto the wafer is maximized. Through increases in both alignment precision and projection accuracy, today""s lithography tools are capable of producing devices with ever decreasing minimum feature size. However, minimum feature size is but one measure of a lithography tool""s utility. Another critical measure is throughput.
Throughput refers to the number of wafers per hour that can be patterned by a lithography system. Every task that must be performed on wafers within a lithography system contributes to the total time required to pattern the wafers, with an associated decrease in throughput. One critical task that must be performed repeatedly within a lithography system is wafer alignment. Wafers must be precisely aligned within a lithography system in order to achieve high levels of overlay accuracy. Unfortunately, alignment precision is usually lost whenever wafers are moved within conventional lithography systems with robots.
What is needed is a system and method for handling wafers within a lithography system that both avoids the loss of alignment caused by conventional robots, while at the same time improving system throughput.
In one embodiment, the present invention includes a lithography system having a lithography patterning chamber, a wafer exchange chamber separated from the lithography patterning chamber by a first gate valve, and at least one alignment load-lock separated from the wafer exchange chamber by a second gate valve. The alignment load-lock includes an alignment stage that aligns a wafer during pump-down. An alignment load-lock according to the present invention can be uni-directional or bi-directional. Likewise, a lithography system according to the present invention can include one or multiple alignment load-locks.
A lithography system according to the present invention can also include a holding load-lock separated from the wafer exchange chamber.
A lithography system according to the present invention can further include an illumination source that emits light having an inspection wavelength, and a camera sensitive to said inspection wavelength. A roof of the alignment load-lock is transparent to the inspection wavelength to allow observation of the wafer contained within the alignment load-lock.
Also included within the alignment load lock according to an embodiment of the present invention are supports for holding a wafer. These supports can be hooks, pins, and the like. An alignment stage is further located within the alignment load lock. The alignment stage is separated from an alignment sub-stage disposed outside of the alignment load-lock by a column extending through a floor of the alignment load-lock. Furthermore, the floor of the alignment load-lock can include a motion feedthrough seal that allows the column to move relative to the floor while preventing gas flow into the alignment load-lock. Such a motion feedthrough seal can include bellows and rotary seals such as ferromagnetic seals.
Further included in an embodiment of the present invention are multiple chucks. The chucks can be electrostatic chucks or vacuum chucks. The chucks can include cutouts for accommodating the wafer supports within the alignment load-lock. The chucks can further include chuck engagement mechanisms for kinematically mounting the chucks to the alignment stage or to a stage located within the lithography patterninging chamber. In critical areas, the chuck engagement mechanisms can be kinematic hemispheres in order to avoid stress and strain, including, for example, hemispheres for engagement with vee-blocks located on the various stages within the lithography system.
In an embodiment of the present invention, the lithography patterninging chamber can include multiple exposure stages.
Also disclosed is a method of patterning a wafer within a lithography system. In an embodiment, the method includes a first step of placing the wafer on supports within an alignment load-lock. In a next step, the wafer is aligned with respect to a chuck while the wafer is supported within the alignment load-lock on the supports. In another step, the wafer is secured to the chuck. And in yet another step, pump-down is performed to create a vacuum within the alignment load-lock.
In a method according to the present invention, pump-down can be performed concurrently with aligning the wafer relative to the chuck. Likewise, pump-down can be performed concurrently with securing the wafer to the chuck subsequent to the alignment step.
A method according to an embodiment of the present invention can also include a step of transporting the chuck and wafer to a lithography patterning chamber. Further fine alignment may be needed in the lithography patterning chamber. Next, a step of performing lithography patterning on the wafer is conducted. Once the lithography patterning is complete, the wafer and chuck are returned to the alignment load-lock area. Once back at the alignment load-lock, the chuck can be removed from the wafer and venting can be performed. The venting can take place while the wafer is being removed from the chuck.
Also disclosed herein is a method of aligning a wafer within an alignment load-lock. In an embodiment, this method includes a first step of placing the wafer on supports within the alignment load-lock. Next, a step of observing the location and orientation of the wafer on the supports within the alignment load-lock is performed. Also performed is a step of moving a chuck so as to align the wafer with respect to the chuck. Once aligned, the chuck is then placed in contact with, and secured to, the wafer. The step of observing the location and orientation of the wafer can be performed by a camera located outside of the alignment load-lock.